The invention relates, in general, to semiconductor devices and, more particularly, to a method of manufacturing a semiconductor device, in which bit lines are formed from aluminum (Al) with a low resistivity, thereby decreasing sheet resistance Rs and solving a RC delay problem.
As devices are more highly integrated, the space between bit lines decreases due to a reduction in the design rule, making it difficult to secure a capacitance value between the bit lines. To secure the capacitance value, a Reactive Ion Etching (RIE) method is used when forming the bit lines in order to lower the height of the bit line.
However, the resistance value is increased due to the lowered height of the bit line, and the capacitance value is increased due to the decreased width of the bit line. Accordingly, the sheet resistance Rs of the bit line increases, RC delay occurs, and the signal operating speed reduces.